Internet-based virtual manufacturing: a verification tool for IC designs

This work is the first step toward the Internet-based “virtual manufacturing”. The problem of statistical design of IC cells, with special emphasis on analog IC design and device mismatch is addressed. A statistical CMOS process/device simulator accessible via user friendly Web interface has been developed. The process is simulated in a statistical (Monte Carlo-type) loop with all kinds of variations, inter-die and intra-die, random and deterministic, taken into account. The input data includes device channel dimensions, orientations and positions on the chip. A statistical sample of chips is simulated. The outputs include SPICE model files with individual models for all simulated devices and a statistical file. A statistical post processor provides statistics of model parameters including correlations and mismatch. These data can be used for verification of manufacturability and optimization of IC designs. The user does not need to know the processing details and has no access to confidential manufacturing-related information