Application-specific hardware accelerator for implementing recursive sorting algorithms

The paper is dedicated to hardware accelerators for data sorting using tree-based recursive algorithms. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model of a hierarchical finite state machine. The paper presents new results in: 1) computational models and hardware architectures; 2) optimization and parallel execution of recursive sorting algorithms; 3) the analysis and comparison of alternative and competitive techniques for implementation of recursive sorting algorithms both in hardware and software. Experiments with the proposed FPGA-based hardware accelerators demonstrate that the performance of sorting operations is increased compared to known implementations.