Title :
Aliasing-free space and time compactions with limited overhead
Author :
Ding, Jin ; Moloney, David ; Wang, Xiaojun
Author_Institution :
Silicon Syst. Ltd., Dublin, Ireland
Abstract :
Space- and time-oriented compactions are to reduce the output response data width and length of circuits under test for built-in self-test technique. In this paper, the space- and time-oriented compaction techniques are considered together. First, the space-oriented data compaction technique is analyzed. We present a scheme, which can compress the data of k-output circuit into 1-bit signature stream with zero-aliasing and zero-performance-degradation for single stuck-line faults. Based on the investigation of the space´s odd-sensitized and space´s even-sensitized faults of the circuits under test, we discuss the compact methods of space´s odd sensitization and space´s even sensitization test responses, respectively. The graph coloring is adopted to decrease space compactor overhead. The coloring complexity is greatly decreased owing to only painting the output notes with respect to the space´s even-sensitized faults. Next, we take into account the time-oriented data compaction scheme. We use the property that a test vector detects multiple faults in the time´s even sensitization response compaction. In the time-oriented compaction approach developed in this paper, an s-bit long data stream can be compressed to an r-bit signature with zero-aliasing, where s≫r. Experimental results are presented to demonstrate the effectiveness of the proposed space- and time-oriented compaction techniques
Keywords :
antialiasing; built-in self test; data compression; integrated circuit testing; logic testing; aliasing-free space compaction; aliasing-free time compaction; built-in self-test technique; even-sensitized faults; graph coloring; odd-sensitized faults; output response data width; signature stream; space compactor overhead; stuck-line faults; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Electronic equipment testing; Painting; Registers; Silicon; System testing;
Conference_Titel :
Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0525-2
DOI :
10.1109/ISQED.2000.838896