Title :
A pre-simulation measure of d.c. design-for-testability fault diagnosis quality
Author :
Worsman, Matthew ; Wong, Mike W T ; Lee, Y.S.
Author_Institution :
Dept. of Electron. & Inf. Eng., Hong Kong Polytech., Kowloon, Hong Kong
Abstract :
Equivalent faults inhibit fault diagnosis by producing indistinguishable test metric measurements. Removal of conditions causing the equivalence in response exhibited by such faults is necessary, if fault diagnosis quality is to be improved. As Design for-Testability (DFT) methodology aims to deliver a degree of fault diagnosis substantially greater than that obtainable testing unassisted by on-chip test specific hardware, designing a DFT scheme with minimal fault equivalence is an issue to be addressed. Presented is a set of simple and inexpensive tests, applied pre-simulation, for identifying catastrophic resistive component faults that cause numerical equivalent d.c. test model responses. Using a biquadratic notch filter modified with a novel DFT scheme, we demonstrate that equivalent fault information is a useful initial measure for assessing the potential increase in fault diagnosis quality obtainable with a DFT scheme
Keywords :
design for testability; fault diagnosis; integrated circuit design; integrated circuit testing; DC DFT fault diagnosis quality; biquadratic notch filter; catastrophic resistive component faults; design-for-testability fault diagnosis; equivalent fault information; minimal fault equivalence; numerical equivalent DC test model responses; pre-simulation measure; Circuit faults; Circuit simulation; Circuit testing; Councils; Design for testability; Design methodology; Electronic equipment testing; Fault diagnosis; Filters; Integrated circuit testing;
Conference_Titel :
Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0525-2
DOI :
10.1109/ISQED.2000.838897