A PT-IGBT with a p-/n+ buffer layer

Author

Ishiko, Masayasu ; Kawaji, Sachiko ; Nishiwaki, Katsuhiko ; Ohnishi, Toyokazu

Author_Institution

R&D Labs., Toyota Central Inc., Aichi, Japan

fYear

2003

fDate

14-17 April 2003

Firstpage

341

Lastpage

344

Abstract

A novel punch-through insulated gate bipolar transistor with a p-/n+ buffer layer was proposed to improve the characteristics of conventional high power IGBT used in motor control inverters at high voltages operation. The new structure with p-floating layer inserted between n- epi and n+ buffer layer shows higher breakdown voltage than that of conventional IGBT structures. We also demonstrate, for the first time, the performance of 900V-200A class IGBTs using this p- floating/n+ buffer structure. As a result of the measurements, the IGBT proposed here shows an on-state voltage of 1.9V at 250A/cm² and the fall time of 350 nsec.

Keywords

automotive electronics; digital simulation; insulated gate bipolar transistors; 1.9 V; 200 A; 350E9 sec; 900 V; PT-IGBT; high voltages operation; higher breakdown voltage; motor control inverters; p-/n+ buffer layer; punch-through insulated gate bipolar transistor; Automotive engineering; Buffer layers; Circuits; Insulated gate bipolar transistors; Intelligent vehicles; Inverters; Mass production; Motor drives; Research and development; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on

Print_ISBN

0-7803-7876-8

Type

conf

DOI

10.1109/ISPSD.2003.1225297

Filename

1225297