DocumentCode :
1953525
Title :
Multi-dimensional packet classification on FPGA: 100 Gbps and beyond
Author :
Qi, Yaxuan ; Fong, Jeffrey ; Jiang, Weirong ; Xu, Bo ; Li, Jun ; Prasanna, Viktor
Author_Institution :
Res. Inst. of Inf. Technol., Tsinghua Univ., Beijing, China
fYear :
2010
fDate :
8-10 Dec. 2010
Firstpage :
241
Lastpage :
248
Abstract :
Multi-dimensional packet classification is a key task in network applications, such as firewalls, intrusion prevention and traffic management systems. With the rapid growth of network bandwidth, wire speed multi-dimensional packet classification has become a major challenge for next-generation network processing devices. In this paper, we present a FPGA-based architecture targeting 100 Gbps packet classification. Our solution is based on HyperSplit, a memory-efficient tree search algorithm. First, we present an efficient pipeline architecture for mapping HyperSplit tree. Special logic is designed to support two packets to be processed every clock cycle. Second, a node-merging algorithm is proposed to reduce the number of pipeline stages without significantly increasing the memory requirement. Third, a leaf-pushing algorithm is designed to control the memory usage and to support on-the-fly rule update. The implementation results show that our architecture can achieve more than 100 Gbps throughput for the 64-byte minimum Ethernet packets. With a single Virtex-6 chip, our approach can handle over 50K rules. Compared with the state-of-the-art multi-core network processor based solutions, our FPGA design offers at least a 10x improvement in throughput performance.
Keywords :
field programmable gate arrays; logic design; reconfigurable architectures; search problems; trees (mathematics); FPGA-based architecture design; HyperSplit tree mapping; bit rate 100 Gbit/s; firewalls; intrusion prevention system; leaf-pushing algorithm; memory-efficient tree search algorithm; minimum Ethernet packets; multicore network processor; network bandwidth; next-generation network processing devices; node-merging algorithm; on-the-fly rule update; single Virtex-6 chip; traffic management systems; wire speed multidimensional packet classification; Algorithm design and analysis; Classification algorithms; Field programmable gate arrays; Memory management; Pipelines; Random access memory; FPGA; Packet classification; Pipeline;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology (FPT), 2010 International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8980-0
Type :
conf
DOI :
10.1109/FPT.2010.5681492
Filename :
5681492
Link To Document :
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