Title :
A new layout optimization methodology for CMOS complex gates
Author :
Chen, C.Y.R. ; Hou, C.Y.
Author_Institution :
Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Abstract :
Efficient algorithms for the layout generation of CMOS complex gates are presented. Heuristics which use the concept of delayed binding are introduced. An optimized net list is decided during the layout generation phase, rather than before. Examples are given showing that this approach can achieve a considerable improvement over previous ones.<>
Keywords :
CMOS integrated circuits; circuit layout CAD; delays; heuristic programming; integrated logic circuits; logic gates; optimisation; CMOS complex gates; delayed binding; efficient algorithms; heuristics; layout optimization methodology; optimized net list; CMOS logic circuits; Delay; Logic functions; MOS devices; Optimization methods; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122530
