A new bi-directional PMOSFET hot-carrier degradation model for circuit reliability simulation

Author

Li, C.C. ; Quader, K.N. ; Minami, E.R. ; Chenming Hu ; Ko, P.K.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

547

Lastpage

550

Abstract

In this paper, the concept of channel shortening is used to model hot-carrier induced PMOSFET drain current degradation. This new approach models the asymmetric drain current degradation in forward and reverse modes of operation and provides the capability to simulate bi-directional stress. We will present the model, its implementation in BERT (BErkeley Reliability Tools), and simulation results of uni- and bi-directionally stressed circuits.<>

Keywords

circuit analysis computing; circuit reliability; digital simulation; hot carriers; insulated gate field effect transistors; semiconductor device models; BERT; BErkeley Reliability Tools; asymmetric drain current degradation; bidirectional PMOSFET; bidirectionally stressed circuits; channel shortening; circuit reliability simulation; forward modes; hot-carrier degradation model; reverse modes; unidirectionally stressed circuits; Circuit reliability; Circuit simulation; Hot carriers; Insulated gate FETs; Semiconductor device modeling; Simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307421

Filename

307421