Peak power reduction in low power BIST

In order to meet the power and reliability constraints, it is important to reduce both average and peak power during BIST operations. In this paper we propose a Low Power Automatic Test Pattern Generator (LPATPG) with peak power. reduction. The technique can be used during on-line testing of large circuits requiring low power consumption. The LPATPG can be implemented using linear cellular automata (CA) with appropriate external weighting logic. While the average power is reduced by finding the optimal signal activities (probabilities of signal switching) at the primary inputs, the peak power is reduced by restricting the number of active primary inputs. Results on ISCAS benchmark circuits show that while achieving high fault coverage, average power reduction up to 90%, peak power reduction up to 37% and energy reduction up to 93% can be achieved (compared to equi-probable random pattern generator by linear cellular automata), and the ratio of the number of high power vectors (vectors violating the power limit) in the LPATPG sequence to the number of high power vectors in the equi-probable random sequence can be as low as 0.44%