Towards fully integrated SiC cascade power switches for high voltage applications

This paper presents an advanced numerical analysis of novel hybrid silicon/SiC multiple cascode configuration. The novel approach is exemplified through a three device cascode Configuration, whereby a 5-20V silicon MOSFET blocks a lateral medium voltage 60-100V SiC JFET, which in turn reverse biases the gate of a vertical high voltage (≥1.2kV) SiC JFET. Furthermore, an elegant solution for the SiC part of the hybrid multiple cascode is also presented. A fully integrated SiC cascoded JFETs chip is proposed and numerically demonstrated. The results obtained through mixed mode simulations for the two cascode configurations are compared.