A high speed pipelined FFT processor

Author

Malladi, Srnivasa R. ; Myneni, Seshagin R. ; Pothana, Pardha V. ; Bayoumi, Magdy A.

Author_Institution

Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA

fYear

1991

fDate

14-17 Apr 1991

Firstpage

1609

Abstract

The authors describe a novel modular design and a VLSI implementation of a bit-serial pipelined fast Fourier transform (FFT) coprocessor. The proposed architecture is based on a distributed hardwired control mechanism. The control of various subunits in the processor is done by local controllers and the synchronization of operations is provided by a global controller. This FFT processor is a custom-built chip which has a built-in self-test (BIST) capability. BIST is provided using a coprocessor to a microprocessor, and the data transfer is controlled by asynchronous signals. A prototype of the proposed processor was implemented in 3-μm SCMOS technology; it can operate at a maximum frequency of 50 MHz. The chip is a 32-pin square package, and it has a total area of 2.2 cm²

Keywords

CMOS integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; pipeline processing; 3.0 micron; 50 MHz; SCMOS technology; VLSI; asynchronous signals; bit-serial coprocessor; built-in self-test; custom-built chip; data transfer; distributed hardwired control; high speed processor; local controllers; microprocessor; modular design; pipelined FFT processor; synchronization; Built-in self-test; Computer architecture; Coprocessors; Digital signal processing chips; Discrete Fourier transforms; Frequency; Pipeline processing; Signal processing algorithms; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on

Conference_Location

Toronto, Ont.

ISSN

1520-6149

Print_ISBN

0-7803-0003-3

Type

conf

DOI

10.1109/ICASSP.1991.150574

Filename

150574