A novel cell structure suitable for a 3 volt operation, sector erase flash memory

A novel flash cell structure named DINOR (DIvided bit-line NOR) whose bit-line is divided into main and sub bit-line, having a unit consisting of one select transistor and 8 stacked gate cells, is proposed. By combining this cell structure and gate-biased FN erase/write operation, we have succeeded in making a cell that has little drain disturb, high over erasure tolerance, low power dissipation, possibility of 3 volt operation, high data transfer rate, and small erase unit, without losing fast random access. All of the disturbs and single-cell endurance characteristics proved to be acceptable. Moreover, using several self-align processes, 2.88 mu m/sup 2/ cell size based on 0.5 mu m CMOS process is realized, which is a 20% cell area reduction compared with the conventional NOR cell.<>