DocumentCode :
1953962
Title :
An efficient compaction algorithm for test vectors of microprocessors and microcontrollers
Author :
Gulati, R.K. ; Goel, D.K.
Author_Institution :
Ford Microelectron. Inc., Colorado Springs, CO, USA
fYear :
1988
fDate :
7-10 Nov. 1988
Firstpage :
378
Lastpage :
381
Abstract :
A compaction algorithm is presented that takes advantage of the fact that repeating patterns in the simulation output of microprocessors and microcontrollers occur due to specific reasons. An instance of each different, multiply-occurring repeating pattern is extracted as a subroutine in an efficient manner, as compared to the ad hoc approaches used earlier. Compaction is then achieved by replacing the repeating patterns by calls to appropriate subroutines. The algorithm has been implemented in a C program, with excellent results obtained. A sample of the results is included.<>
Keywords :
circuit analysis computing; digital simulation; integrated circuit testing; microcontrollers; microprocessor chips; subroutines; C program; compaction algorithm; microcontrollers; microprocessors; repeating patterns; simulation output; subroutine; test vectors; Algorithms; Compaction; Logic testing; Microcontrollers; Microelectronics; Microprocessors; Pins; Production; Springs; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
Type :
conf
DOI :
10.1109/ICCAD.1988.122532
Filename :
122532
Link To Document :
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