Title :
A high-speed low-cost DCT architecture for HDTV applications
Author :
Mou, Zhi-Jian ; Jutand, Francis
Author_Institution :
Dept. of Electron., Telecom Paris Univ., France
Abstract :
An eight-point DCT (discrete cosine transform) architecture is presented. The modified Booth encoding is employed to process two bits per cycle. Therefore, the internal clock frequency is the same as the sampling rate. Carry-save adders are applied to the accumulation of partial results. The computing speed is thus highly increased. The architecture is completely hardwired in order to remove unnecessary ROMs. The resulting scheme will be able to satisfy the stringent HDTV (high-definition television) requirements with only a modest quantity of hardware
Keywords :
digital arithmetic; encoding; high definition television; transforms; HDTV; carry-save adders; computing speed; discrete cosine transform; eight-point DCT; high speed architecture; high-definition television; internal clock frequency; modified Booth encoding; sampling rate; Clocks; Computer architecture; Discrete cosine transforms; Encoding; Frequency; HDTV; Hardware; Read only memory; Sampling methods; TV;
Conference_Titel :
Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7803-0003-3
DOI :
10.1109/ICASSP.1991.150575
