SOPC design for implementation of overcurrent relay

Author

Kumar, Vishal ; Prabhu, Sanjay ; Gupta, I. ; Gupta, H.O.

Author_Institution

Electr. Eng. Dept., Indian Inst. of Technol. Roorkee

fYear

0

fDate

0-0 0

Abstract

Design for implementation of an overcurrent relay as a system on programmable chip (SOPC) is presented. FPGA (field programmable gate arrays) is used for the system on chip (SOC) application to achieve a SOPC for the proposed design. The design is suitable for distribution or sub-transmission networks and can behave as extreme inverse or very inverse type of time overcurrent relay. The proposed relay follows standard inverse-time characteristics according to IEEE standard C37.112-1996. The details of hardware and software used for the design implementation are presented. Performance of the designed relay has been checked; the results from tests performed are also included in the paper

Keywords

IEEE standards; distribution networks; field programmable gate arrays; hardware-software codesign; overcurrent protection; relay protection; system-on-chip; transmission networks; FPGA; IEEE standard C37.112-1996; SOC; digital relay; distribution network; field programmable gate arrays; hardware-software design; inverse-time characteristics; overcurrent relay; sub-transmission network; system on chip; system on programmable chip; Application specific integrated circuits; Digital relays; Field programmable gate arrays; Hardware; Logic devices; Power system protection; Power system relaying; Programmable logic arrays; Protective relaying; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Power India Conference, 2006 IEEE

Conference_Location

New Delhi

Print_ISBN

0-7803-9525-5

Type

conf

DOI

10.1109/POWERI.2006.1632525

Filename

1632525