Title :
Degradation mechanism of polysilicon TFTs under DC stress
Author :
Kato, N. ; Yamada, T. ; Yamada, S. ; Nakamura, T. ; Hamano, T.
Author_Institution :
Electron. Imaging & Devices Res. Lab., Fuji Xerox Co. Ltd., Kanagawa, Japan
Abstract :
The degradation of polysilicon thin film transistors was investigated under DC stress. There was a strong relationship between increase of threshold voltage and power consumption under stressing. The channel was found to reach high temperature by Joule heat because of poor thermal conductivity of the quartz substrate. It is shown that this temperature rise accelerates the degradation caused by gate stress.<>
Keywords :
elemental semiconductors; semiconductor device testing; silicon; thin film transistors; DC stress; Joule heat; Si; degradation mechanism; gate stress; polysilicon TFTs; power consumption; temperature rise; thermal conductivity; threshold voltage; Semiconductor device testing; Silicon; Thin film transistors;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307451
