Title :
A built-in self-test PLA design with full fault coverage
Author :
Rajashekhara, T.N. ; Nale, A.S.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
Abstract :
A built-in self-test (BIST) PLA (programmable logic array) design using a new technique for on-chip storage and retrieval of the compressed signature of a fault-free PLA is proposed. The design uses function-independent test input sequences, and provides function-independent test responses. Additional features of the proposed BIST PLA design are: (1) simplified implementation of test evaluator, (2) reduced test length (2ninp test inputs for a PLA with ni inputs and n p product lines), (3) full fault coverage in the naked PLA, (4) crosspoint fault locatability, and (5) only three extra pinouts. The proposed input decoder augmentation will not result in any performance degradation. With these features, the proposed design is more efficient than other BIST PLA designs reported in the literature
Keywords :
built-in self test; logic arrays; logic design; logic testing; PLA design; built-in self-test; compressed signature; crosspoint fault locatability; full fault coverage; function-independent test input sequences; function-independent test responses; input decoder augmentation; naked PLA; on-chip storage; performance degradation; pinouts; programmable logic array; test evaluator; test length; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Decoding; Degradation; Logic arrays; Logic functions; Programmable logic arrays;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101791
