A buried capacitor DRAM cell with bonded SOI for 256 M and 1 Gbit DRAMs

This paper describes a novel DRAM cell structure using bonded SOI. The cell capacitor is flexibly formed like a stack-capacitor, but buried under the silicon layer. Thus, both a large Cs and small cell size are obtained. Moreover, using a PMOS cell transistor whose back-surface is shielded by a cell plate, the cell leakage current is reduced to 1 fA/cell, resulting in good data retention. Accordingly, a simple scaling of this structure realizes 256 M and 1 Gbit DRAMs.<>