DRAM variable retention time

Author

Restle, P.J. ; Park, J.W. ; Lloyd, B.F.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

807

Lastpage

810

Abstract

A DRAM bit has variable retention time (VRT) when the memory cell leakage, which determines how long a cell can retain information, varies with time. This paper reports on a study of VRT in cells from 4Mbit and 16 Mbit DRAM chips produced by a variety of manufacturers and in a number of technologies including trench capacitor and stacked capacitor cells. VRT cells were found on all chips. This paper describes the detection and characterization of two classes of VRT cells: 2-state and multi-state VRT cells, and presents a model containing 4 activation energies and 3 pre-factors that describes the temperature dependence of retention times and transition rates for the 2-state VRT cells. A description of new test techniques and the analysis needed to detect and study VRT are provided as well as examples from typical 4 Mbit chips.<>

Keywords

DRAM chips; VLSI; cellular arrays; integrated circuit testing; time measurement; 16 Mbit; 4 Mbit; DRAM; activation energies; memory cell leakage; multi-state VRT cells; stacked capacitor; temperature dependence; test techniques; transition rates; trench capacitor; variable retention time; Cellular logic arrays; DRAM chips; Integrated circuit testing; Time measurement; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307481

Filename

307481