Title :
A high-performance quadruple well, quadruple poly BiCMOS process for fast 16 Mb SRAMs
Author :
Hayden, J.D. ; Woo, M.P. ; Taft, R.C. ; Pelley, P. ; Nguyen, B.-Y. ; Mazure, C. ; Kenkare, P.U. ; Kemp, K. ; Subrahmanyan, R. ; Sitaram ; Lin, J.-H. ; Ko, J. ; King, C. ; Gunderson, C. ; Kirsch, H.C.
Author_Institution :
Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA
Abstract :
An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<>
Keywords :
BiCMOS integrated circuits; SRAM chips; integrated circuit technology; photolithography; 1 micron; 16 Mbit; BiCMOS process; MOSFET transistors; PELOX isolation; SER improvement; Si; double polysilicon bipolar transistor; fast 16 Mb SRAMs; high-performance BiCMOS technology; i-line lithography; i-line phase-shift lithography; polysilicon TFT; quadruple poly process; quadruple well structure; scaled parasitics; self-aligned contacts; soft error rate; split word-line bitcell architecture; thin-film polysilicon transistor; BiCMOS integrated circuits; Integrated circuit fabrication; Photolithography; SRAM chips;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307483
