High reliability and high performance 0.35 mu m gate-inverted TFT´s for 16 Mbit SRAM applications using self-aligned LDD structures

Author

Liu, C.T. ; Lee, K.H. ; Yu, C.H.D. ; Sung, J.J. ; Nagy, W.J. ; Kornblit, A. ; Kook, T. ; Olasupo, K.R. ; Druckenmiller, R.O. ; Fu, C.C. ; Molloy, S.J.

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

823

Lastpage

826

Abstract

A simple self-aligned LDD structure is utilized in gate-inverted TFT´s. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16 Mbit SRAM´s or beyond. We report on the following: fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35 mu m*0.35 mu m devices and their aging and temperature performance; a high I/sub ON//I/sub OFF/ ratio of 1.2*10/sup 8/ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of I/sub ON/; and considerations of device scaling and process margins.<>

Keywords

SRAM chips; circuit reliability; field effect integrated circuits; insulated gate field effect transistors; integrated circuit technology; thin film transistors; 0.35 micron; 16 Mbit; I-V characteristics; SRAM applications; aging; fabrication; gate-inverted TFT; high performance; high reliability; self-aligned LDD structures; temperature performance; Circuit reliability; FET integrated circuits; Insulated gate FETs; Integrated circuit fabrication; SRAM chips; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307484

Filename

307484