Title :
Dual (n/sup +//p/sup +/) polycide interconnect technology using poly-Si/WSi2/poly-Si structure and post B/sup +/ implantation
Author :
Fujii, T. ; Hashimoto, S. ; Naito, Y. ; Hirofuji, Y.
Author_Institution :
Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Moriguchi, Japan
Abstract :
Formation of low resistance p/sup +/ contact was the most difficult problem for dual(n/sup +//p/sup +/) polycide interconnect by which both n/sup +/ contacts and p/sup +/ contacts are directly connected. To solve this problem, we have developed a new technology with a sandwiched poly-Si/WSi2/poly-Si structure, and a post B/sup +/ implantation over the entire polycide including both p/sup +/ and n/sup +/ regions. As a result, this new technology provides sufficiently low resistance for both p/sup +/ and n/sup +/ contacts independent of the spacing distance between p/sup +/ and n/sup +/ regions even after 900 degrees C annealing for 90 minutes and the compact layout of CMOS circuit is made possible while maintaining compatibility with conventional high temperature processes including the economical BPSG flow.<>
Keywords :
CMOS integrated circuits; annealing; boron; contact resistance; diffusion in solids; integrated circuit technology; ion implantation; metallisation; semiconductor-metal boundaries; silicon; tungsten compounds; 90 min; 900 C; CMOS circuit metallisation; IC fabrication; Si:B-WSi/sub 2/:B-Si:B; compact layout; dual(n/sup +//p/sup +/) polycide interconnect; low resistance p/sup +/ contact; n/sup +/ contacts; poly-Si/WSi2/poly-Si structure; polysilicon; post B/sup +/ implantation; Annealing; Boron; CMOS integrated circuits; Contact resistance; Diffusion processes; Integrated circuit fabrication; Ion implantation; Metallization; Semiconductor-metal interfaces; Silicon; Tungsten compounds;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307489
