Reverse Elevated Source/Drain (RESD) MOSFET for deep submicron CMOS

Author

Pfiester, J.R. ; Woo, M. ; Fitch, J.T. ; Schmidt, J.

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

885

Lastpage

888

Abstract

A new Reverse Elevated Source/Drain (RESD) CMOS process has been developed as part of a deep submicron CMOS technology featuring ultra-shallow source/drain junctions with reversed (with respect to epi formation) phosphorus LDD implantation. This new structure utilizes disposable nitride spacers to define the selective silicon offset from the gate edge prior to LDD implantation. Since the LDD junctions are not exposed to the high temperature prebake and deposition conditions, shallow phosphorus junctions provide improved short-channel behavior while maintaining good hot-carrier protection.<>

Keywords

CMOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; ion implantation; CMOS technology; deep submicron CMOS; disposable nitride spacers; gate edge; hot-carrier protection; reverse elevated source/drain MOSFET; reversed phosphorus LDD implantation; selective silicon offset; short-channel behavior; ultra-shallow source/drain junctions; CMOS integrated circuits; Insulated gate FETs; Integrated circuit fabrication; Ion implantation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307498

Filename

307498