Title :
High performance deep submicron buried channel PMOSFET using P/sup +/ poly-Si spacer induced self-aligned ultra shallow junctions
Author :
Chang, P.S.-T. ; Kohyama, Y. ; Kakuma, M. ; Sudo ; Asao, Y. ; Kumagai, J. ; Matsuoka, F. ; Ishiuchi, H. ; Sawada, S.
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron applications. By using this new device structure, the current drivability of a 0.3 mu m PMOSFET is increased by about 40%. This significant increase in current drivability can be attributed to the parasitic resistance reduction due to the formation of P-type inversion layers under the two P+ poly-Si sidewall spacers. Because of the work function difference between the N+ poly-Si gate electrode and the P+ poly-Si spacers, the Si surface under the P+ poly-Si spacers is always more inverted than the channel. As a result, the parasitic resistance is always much lower than the channel resistance. Furthermore, those induced inversion layers act as ultra shallow junctions (>
Keywords :
insulated gate field effect transistors; inversion layers; work function; 0.3 micron; P-type inversion layers; P/sup +/ polysilicon spacer; Si; current drivability; deep submicron buried channel PMOSFET; parasitic resistance reduction; self-aligned ultra shallow junctions; short-channel effects; sidewall spacers; work function difference; Insulated gate FETs; Inversion layers; Work function;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307503
