Title :
Design considerations of SOI digital CMOS VLSI
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
This paper reviews the recent advances of SOI for CMOS VLSI memory and logic applications with particular emphasis on the design issues and advantages resulting from the unique SOI device structure. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. The impact of floating body effects in partially-depleted devices on circuit operation, stability, and functionality are addressed. The use of smart body contacts to improve the power and delay performance are discussed. Global design issues for high-performance microprocessor applications are addressed.
Keywords :
CMOS logic circuits; CMOS memory circuits; DRAM chips; SRAM chips; VLSI; circuit stability; integrated circuit design; microprocessor chips; silicon-on-insulator; DRAMs; SOI CMOS VLSI logic applications; SOI CMOS VLSI memory applications; SOI device structure; SOI digital CMOS VLSI; SRAMs; Si-SiO/sub 2/; artially-depleted devices; circuit functionality; circuit operation; circuit stability; delay performance; design considerations; digital CMOS logic circuits; dynamic random access memories; floating body effects; global design issues; high-performance microprocessor applications; power performance; smart body contacts; static random access memories; CMOS logic circuits; CMOS technology; Capacitance; Inverters; Logic devices; MOSFET circuits; Random access memory; Threshold voltage; Uncertainty; Very large scale integration;
Conference_Titel :
SOI Conference, 1998. Proceedings., 1998 IEEE International
Conference_Location :
Stuart, FL, USA
Print_ISBN :
0-7803-4500-2
DOI :
10.1109/SOI.1998.723072
