DocumentCode
1955713
Title
A tool for hierarchical test generation
Author
Kruger, G.
Author_Institution
Nixdorf Comput. AG, Paderborn, West Germany
fYear
1988
fDate
7-10 Nov. 1988
Firstpage
420
Lastpage
423
Abstract
An extended system for automatic test generation and its algorithm are presented. In a hierarchical mixed-level approach (from gate- to system-level), test patterns for sequential circuits of arbitrary depth, and even test programs for either external or self-test of microprocessor boards or processor systems, can be generated automatically. In a complete hierarchy, lower bounds for test coverage are easily computable. Applications in real production-line testing have shown good results.<>
Keywords
automatic testing; circuit analysis computing; integrated circuit testing; logic testing; microprocessor chips; sequential circuits; automatic test generation; external testing; gate level approach; hierarchical mixed-level approach; microprocessor boards; production-line testing; self testing; sequential circuits; system level approach; test coverage lower bounds; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Hardware; Microprocessors; Sequential analysis; Software testing; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-0869-2
Type
conf
DOI
10.1109/ICCAD.1988.122541
Filename
122541
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