Research on deep RIE-based through-Si-via micromachining for 3-D system-in-package integration

This paper reports the designing/simulation and experimental investigation into the Deep RIE-based micro-fabrication of through-Si-via (TSV) which acts as the vital vertical interconnect for compact 3-D system-in-package integration. An in-house developed process simulator based on cell/string evolution algorithm and physical modeling is used to explore suitable DRIE conditions for drilling vias with various sections, especially those with tapered profile. The effectiveness of the simulator is verified with process trials. Optimal deposition parameters are obtained for conformal formation of insulation, barrier and seed layers for electro-plating via filling. Combined with additives, Periodic Pulse Reverse current plating is utilized for satisfying bottom-up blind-via filling. The research have laid firm groundwork for the demonstration of the prospect of 3-D packaging based microsystem integration, combining heterogeneous micro/nano devices with ICs, in consumer, industrial and defense electronics.