Modeling of Parasitic Fringing Capacitance in Multifin Trigate FinFETs

In this brief, we analyze the effects of geometrical parameters on the parasitic fringing capacitance of sub 22-nm multifin FinFETs. An analytical model is proposed to compute the fringing capacitance using a conformal mapping technique. To minimize the number of model fitting parameters, nondimensionalization technique is used. The proposed model for gate to source/drain fringing capacitance considers the fin number, whether the fin location is at the edge of the gate, and the source/drain pad that connects the fins. The accuracy of this model is verified with a 2- and 3-D field solver, Raphael.