Title :
Novel Method of Digital Clock Frequency Multiplication and Division Using Floating Point Arithmetic
Author :
Chidambaram, S. ; Chaitanya, V.S.
Author_Institution :
Manipal Centre for Inf. Sci., Manipal Univ., Manipal, India
Abstract :
A digital clock frequency multiplier, divisor using floating point arithmetic which generates the output clock with almost zero frequency error has been presented. The circuit has an unbounded multiplication and division factor range and low lock time. A low power mechanism has been incorporated to ensure that the overall power consumption of the circuit is less. The circuit has been designed in TSMC 65nm CMOS process for an input reference time of 0.01ns and has been verified with random multiplication factor values.
Keywords :
CMOS digital integrated circuits; clocks; floating point arithmetic; frequency multipliers; TSMC CMOS process; digital clock frequency division; digital clock frequency multiplication; digital clock frequency multiplier; division factor; floating point arithmetic; low power mechanism; size 65 nm; time 0.01 ns; unbounded multiplication; zero frequency error; Adders; Clocks; Frequency conversion; Frequency synthesizers; Phase locked loops; Synchronization; Time-frequency analysis; clock; clock division; clock multiplication;
Conference_Titel :
Intelligent Systems Modelling & Simulation (ISMS), 2013 4th International Conference on
Conference_Location :
Bangkok
Print_ISBN :
978-1-4673-5653-4
DOI :
10.1109/ISMS.2013.22
