An implementation of a hierarchical generalized transversal digital filter

Author

Kadowaki, Yukio ; Nakamura, Syogo ; Kawahashi, Akiyoshi

Author_Institution

LSE Res. & Dev. Center, Osaka, Japan

fYear

1991

fDate

14-17 Apr 1991

Firstpage

1169

Abstract

The authors have implemented the two-level hierarchical generalized transversal FIR filter. This chip included nine subfilters and four tapping parts. Each subfilter had exactly the same filter characteristics and the coefficients of each tapping part were the same. This highly parallel structure allowed the reduction of the number of control bits, the number of filter sequences, the chip size, and the operation time. It only needed up to 32 words and 16 bits of machine-level control sequence. Up to 21-MHz clock speed and 3 MHz sampling speed was available. The 5.4×5.5 mm chip was fabricated using 1.2-μm double-level metal CMOS technology with 44 pins flat or PLCC package

Keywords

CMOS integrated circuits; VLSI; digital filters; 1.2 micron; 16 bit; 21 MHz; 3 MHz; PLCC package; VLSI; chip size; clock speed; coefficients; control bits; double-level metal CMOS technology; filter characteristics; filter sequences; hierarchical generalised digital filters; operation time; parallel structure; sampling speed; subfilters; tapping parts; transversal FIR filter; CMOS technology; Digital filters; Finite impulse response filter; Large scale integration; Level control; Read only memory; Research and development; Sampling methods; Size control; Transversal filters;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on

Conference_Location

Toronto, Ont.

ISSN

1520-6149

Print_ISBN

0-7803-0003-3

Type

conf

DOI

10.1109/ICASSP.1991.150585

Filename

150585