An 11-bit Two-Stage Hybrid-DAC for TFT LCD Column Drivers

Author

Ping-Yeh Yin ; Chih-Wen Lu ; Chih-yu Hsu ; Yo-Sheng Lin

Author_Institution

Dept. of Electr. Eng., Nat. Chi Nan Univ., Puli, Taiwan

fYear

2013

fDate

29-31 Jan. 2013

Firstpage

631

Lastpage

635

Abstract

This paper proposes an 11-bit two-stage hybrid-DAC for high-color-depth LCD column drivers. To save the die area, the proposed DAC is composed of a 7-bit RDAC and a 4-bit cyclic-DAC to render an 11-bit resolution. The worst DNL/INL from post-layout simulation is 0.28/0.34 LSB with 1 LSB = 2.2 mV. A three-stage class-B operational amplifier is connected as a unity-gain buffer to drive highly capacitive column lines of LCD panel. The buffer´s settling time to settle within 0.2% of the final voltage is less than 4 us. This hybrid-DAC prototype is implemented using 0.35-um CMOS technology with a chip size of 1.36 mm².

Keywords

CMOS analogue integrated circuits; buffer circuits; circuit simulation; digital-analogue conversion; driver circuits; liquid crystal displays; operational amplifiers; thin film transistors; CMOS technology; DNL/INL; LCD panel; RDAC; TFT LCD column driver; capacitive column line; cyclic-DAC; die area; high-color-depth LCD column driver; post-layout simulation; size 0.35 mum; three-stage class-B operational amplifier; two-stage hybrid-DAC; unity-gain buffer; word length 11 bit; word length 4 bit; word length 7 bit; Capacitors; Clocks; Interpolation; Operational amplifiers; Resistors; Transistors; DAC; LCD; column driver; cyclic-DAC; operatioal amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Systems Modelling & Simulation (ISMS), 2013 4th International Conference on

Conference_Location

Bangkok

ISSN

2166-0662

Print_ISBN

978-1-4673-5653-4

Type

conf

DOI

10.1109/ISMS.2013.44

Filename

6498348