A dormant subcircuit model for maximizing iteration latency

An approach for modeling dormant subcircuits is presented that utilizes iteration latency to provide speed improvements that are comparable to the potential speed improvements of an independent time step approach. This scheme minimizes the work required on the first iteration at a time point, which is the normal limiting factor in iteration latency schemes. However, since simulations are performed for each subcircuit at each time point, the penalty for backing up when truncation error is unacceptable is minimized.<>