Title :
The impact of intermetal dielectric layer and high temperature bake test on the reliability of nonvolatile memory devices
Author :
Sakagami, Eiji ; Arai, Norihisa ; Tsunoda, Hiroaki ; Egawa, Hidemitsu ; Yamaguchi, Yoshiko ; Kamiya, Eiji ; Takebuchi, Masataka ; Yamada, Kenji ; Yoshikawa, Kuniyoshi ; Mori, Seiichi
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
This paper describes the effects of water-related species contained in intermetal dielectric layers on the reliability of nonvolatile memory devices. Charge loss of the cells and hot-carrier (HC) lifetime degradation of peripheral N-channel MOSFETs due to the high temperature bake test are accelerated by the water-related species in the intermetal dielectric layer. The relation between the charge loss and the HC-lifetime degradation and the mechanism involved are discussed. Appropriate dielectric structures to minimize such degradation have been proposed for nonvolatile memory devices with double-metal structure and scaled narrow first metal gaps.<>
Keywords :
CMOS integrated circuits; EPROM; circuit reliability; hot carriers; integrated circuit testing; integrated memory circuits; moisture; cell charge loss; dielectric structures; double-metal structure; high temperature bake test; hot-carrier lifetime degradation; intermetal dielectric layer; nonvolatile memory devices; peripheral N-channel MOSFETs; reliability; scaled narrow first metal gaps; water-related species; CMOS technology; Circuit testing; Degradation; Dielectric devices; Dielectric losses; Hot carriers; MOSFETs; Nonvolatile memory; Plasma temperature; Semiconductor device reliability;
Conference_Titel :
Reliability Physics Symposium, 1994. 32nd Annual Proceedings., IEEE International
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-1357-7
DOI :
10.1109/RELPHY.1994.307812
