Title :
Reduction of crystalline defects to 50/cm/sup 2/ in epitaxial layers over porous silicon for ELTRAN/sup R/ process
Author :
Sato, N. ; Ishii, S. ; Matsumura, S. ; Ito, M. ; Nakayama, J. ; Yonehara, T.
Author_Institution :
Canon Inc., Kanagawa, Japan
Abstract :
As the design rules of large scale integrated circuits (LSIs) progress, excellent gate oxide integrity (GOI) is demanded despite the requirement for thinner gate oxides. Crystal originated particles (COPs) are currently reported as killer defects for GOI on Czochralski-silicon (CZ-Si) wafers; however, an epitaxial layer on the CZ substrate gives quite good GOI characteristics because of the significantly small amount of COPs in it. It is expected that the epitaxial layer would be used in silicon-on-insulator (SOI), which is one of the candidates for high speed and low power consumption LSIs. We have already reported the epitaxial layer transfer (ELTRAN) method (Yonehara et al, 1994, and Sato et al, 1995), in which the epitaxial layer on porous Si was transferred on to a handle wafer to form an SOI wafer by bonding and etching back of porous Si with extremely high etching selectivity. In this paper, it is reported that the density of stacking faults, which is the major defect in these wafers, is significantly reduced to 50/cm/sup 2/ by controlling both the porous structure and the prebaking step before growth.
Keywords :
dielectric thin films; elemental semiconductors; etching; integrated circuit reliability; large scale integration; porous semiconductors; semiconductor epitaxial layers; semiconductor growth; silicon; silicon-on-insulator; vapour phase epitaxial growth; wafer bonding; COPs; CZ substrate; CZ-Si wafers; Czochralski-silicon wafers; ELTRAN process; GOI characteristics; LSI design rules; LSI power consumption; LSI speed; SOI; SOI wafer; Si; Si-SiO/sub 2/; bond/etch-back SOI; crystal originated particles; crystalline defect reduction; epitaxial layer; epitaxial layer transfer method; epitaxial layers; etching selectivity; gate oxide integrity; gate oxide thickness; handle wafer; killer defects; large scale integrated circuits; porous Si; porous silicon; porous structure; prebaking step; silicon-on-insulator; stacking fault density; Circuit faults; Crystallization; Energy consumption; Epitaxial layers; Etching; Large scale integration; Silicon on insulator technology; Stacking; Substrates; Wafer bonding;
Conference_Titel :
SOI Conference, 1998. Proceedings., 1998 IEEE International
Conference_Location :
Stuart, FL, USA
Print_ISBN :
0-7803-4500-2
DOI :
10.1109/SOI.1998.723078