Suppression of Si etching during hydrogen annealing of silicon-on-insulator

Generally, polishing is employed as the final treatment of silicon-on-insulator (SOI) at the expense of SOI thickness reduction, because surface microroughness affects the gate oxide integrity. Hydrogen annealing of SOI wafers (Sato and Yonehara, 1994) was originated to replace the polishing, and was traced by several groups. This novel method is advantageous in that there is no thickness reduction in principle. However, in view of the Si etching during hydrogen annealing, various etching rates have been reported in the literature, leading to the question of how much Si is consumed or how much SOI thickness reduction is suppressed. In this paper, Si etching during hydrogen annealing is investigated by using ELTRAN wafers, which are fabricated by transferring epitaxial layers on porous Si on to handle wafers. The lowest reported etching rate to date is achieved.