Title :
Electrical characteristics of the interface between the top Si and buried oxide in ITOX-SIMOX wafers
Author :
Nakashima, S. ; Takahashi, M. ; Kodate, J. ; Ohno, T. ; Izumi, K.
Author_Institution :
NTT Syst. Electron. Labs., Atsugi, Japan
Abstract :
Summary form only given. High-quality ITOX-SIMOX (internal thermal oxidation-SIMOX) wafers (Nakashima et al, 1994) have been used for the fabrication of 0.25 /spl mu/m fully-depleted CMOS-SIMOX LSIs (Ino et al, 1996). In fully-depleted devices, device performance strongly depends on the quality of the interface between the top Si and the buried oxide (top Si-buried oxide interface) as well as that of the gate oxide-top Si interface. However, there are few reports on the electrical characteristics of the top Si-buried oxide interface. Accordingly, we fabricated a buried MOS diode, which has a P/sup +/ gate beneath the buried oxide, in ITOX-SIMOX wafers and investigated the electrical characteristics of the interface. The obtained results reveal that the fixed charge density Q/sub f//q and the interface trap density D/sub it/ are extremely small, and are comparable to those of thermal oxide. These results indicate that the ITOX-SIMOX wafer has a high quality top Si-buried oxide interface, and the reduced pinhole density and high quality interface of ITOX-SIMOX wafers are useful for the fabrication of fully-depleted CMOS-SIMOX LSIs.
Keywords :
CMOS integrated circuits; MOSFET; SIMOX; buried layers; electronic density of states; integrated circuit testing; interface states; large scale integration; oxidation; 0.25 micron; ITOX-SIMOX wafers; Si; SiO/sub 2/-Si; buried MOS diode; buried MOS diode P/sup +/ gate; buried oxide; device performance; electrical characteristics; fixed charge density; fully-depleted CMOS-SIMOX LSIs; fully-depleted MOSFETs; fully-depleted devices; gate oxide-top Si interface; interface electrical characteristics; interface quality; interface trap density; internal thermal oxidation-SIMOX wafers; pinhole density; thermal oxide; top Si-buried oxide interface; Annealing; Capacitance; Capacitance-voltage characteristics; Diodes; Electric variables; Laboratories; MOSFETs; Photonic band gap; Substrates; Voltage;
Conference_Titel :
SOI Conference, 1998. Proceedings., 1998 IEEE International
Conference_Location :
Stuart, FL, USA
Print_ISBN :
0-7803-4500-2
DOI :
10.1109/SOI.1998.723082