Clock and data recovery for a 6 Gbps SerDes receiver

This paper presents the design and implementation of a 6 Gbps clock and data recovery (CDR) system for Serial Advanced Technology Attachment (SATA) standard. The CDR incorporates half rate phase detector and is realized using a 2 loop PLL consisting of a coarse loop and a fine loop. Fast frequency acquisition is acquired through coarse loop and fine phase alignment is performed through a half rate fine loop. While the coarse loop can recover clock ranging from 2.5 GHz to 3.2 GHz the fine loop has an acquisition range of 200 KHz. The design has been implemented in IBM 0.13um CMOS technology. Verilog AMS and Matlab were used for front end design and Cadence for schematic and layout implementation. The overall silicon area of the CDR is approximately 108 × 244 um² excluding loop filter capacitors.