A new DSP architecture suited for image analysis

Author

Oto, Takeshi ; Kitagaki, Kazukuni ; Demura, Tatsuhiko ; Araki, Yoshitsugu ; Takada, Tomoji

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1991

fDate

14-17 Apr 1991

Firstpage

1181

Abstract

A DSP architecture suited for processing in the field of image analysis, which is placed between image preprocessing and image understanding, is described. The DSP, consisting of a flexible EU (execution unit) and hardwired AGUs (address generation units) with several well-considered addressing modes, achieved flexible capability for various algorithms in the image analysis field without complex sequence control. A programmable PLL which can generate the internal clock signal with high frequency has been implemented, and high performance has been achieved in cases of intensive calculations

Keywords

computerised picture processing; digital signal processing chips; phase-locked loops; DSP architecture; DSP chips; address generation units; addressing modes; algorithms; execution unit; high frequency; image analysis; image preprocessing; image understanding; internal clock signal; programmable PLL; Digital signal processing; Histograms; Image analysis; Image edge detection; Image sequence analysis; Labeling; Phase locked loops; Signal processing; Signal processing algorithms; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on

Conference_Location

Toronto, Ont.

ISSN

1520-6149

Print_ISBN

0-7803-0003-3

Type

conf

DOI

10.1109/ICASSP.1991.150590

Filename

150590