DocumentCode
1957587
Title
Architectural support for greater predictability in real-time systems
Author
Gopalakrishnan, Sathish
Author_Institution
Univ. of British Columbia, Vancouver, BC, Canada
fYear
2009
fDate
23-26 Aug. 2009
Firstpage
985
Lastpage
985
Abstract
A real-time system is characterized by computational tasks that need to complete within well-defined time durations. Scheduling policies help guarantee deadlines, but scheduling policies and the analysis associated with them need exact information to guarantee timing correctness. This exact information includes the worst-case execution time of tasks in the system. Existing architecture techniques (caches, superscalar out-of-order execution) improve the average case performance of a computer system but complicate the estimation of worst-case execution times. In the talk I will discuss some recent techniques for estimating WCETs and some techniques for more predictable execution, including the use of scratchpad memories.
Keywords
real-time systems; scheduling; architectural support; architecture techniques; computer system; real-time systems; scheduling policies; superscalar out-of-order execution; timing correctness; worst-case execution time; Computer architecture; Information analysis; Out of order; Processor scheduling; Real time systems; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers and Signal Processing, 2009. PacRim 2009. IEEE Pacific Rim Conference on
Conference_Location
Victoria, BC
Print_ISBN
978-1-4244-4560-8
Electronic_ISBN
978-1-4244-4561-5
Type
conf
DOI
10.1109/PACRIM.2009.5291233
Filename
5291233
Link To Document