DocumentCode
1957595
Title
Synthesis of analog CMOS circuits
Author
Shanker, K. Ravi ; Vasudevan, V.
Author_Institution
SGS-Thomson Microelectron., Noida, India
fYear
1997
fDate
4-7 Jan 1997
Firstpage
439
Lastpage
444
Abstract
In this paper we describe an efficient method for transistor sizing in cell level analog circuits. An equation based method is used. SPICE quality device models are used and the sizing problem is posed as an optimisation problem. KCL, KVL and matching constraints are taken in to account in the formulation of the optimisation problem without explicitly introducing them as constraints as was done previously. A tool developed based on this method has been used to synthesise and study performance trade-offs in various CMOS op amps
Keywords
CMOS analogue integrated circuits; SPICE; VLSI; circuit CAD; circuit optimisation; integrated circuit design; operational amplifiers; CMOS op amps; KCL constraints; KVL constraints; SPICE quality device models; analog CMOS circuits; cell level analog circuits; equation based method; matching constraints; optimisation problem; transistor sizing; Analog circuits; CMOS analog integrated circuits; Circuit simulation; Circuit synthesis; Equations; Kirchhoff´s Law; Microelectronics; SPICE; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location
Hyderabad
ISSN
1063-9667
Print_ISBN
0-8186-7755-4
Type
conf
DOI
10.1109/ICVD.1997.568173
Filename
568173
Link To Document