Title :
Reducing non-optimal LRU decision frequency in chip multiprocessors
Author :
Baniasadi, Amirali ; Deris, Kaveh Jokar
Author_Institution :
Electr. & Comput. Eng., Univ. of Victoria, Victoria, BC, Canada
Abstract :
Least recently used (LRU) is a widely used replacement policy as it offers simplicity and relatively acceptable performance. However, there is a considerable performance gap between LRU and Belady´s theoretical optimal replacement policy in highly associative caches. We study non-optimal LRU decisions (NODs) in chip multiprocessors and investigate NOD distribution within multithreaded applications. We introduce hasty blocks (H-blocks) and predictable blocks (P-blocks) as more inclusive extensions of previously suggested classifications. Based on our findings we present speculative replacement algorithm (SRA) to identify and reduce NOD frequency. We discuss implementation issues and show that with a small 1k entries table we could successfully identify about 90% of H-blocks and half of the P-Blocks. When SRA algorithm is combined with previously suggested techniques it reduces an extra 7% of the cache miss rate on average.
Keywords :
cache storage; microprocessor chips; multi-threading; multiprocessing systems; NOD distribution; NOD frequency; SRA algorithm; cache miss rate; chip multiprocessors; hasty blocks; least recently used; multithreaded application; nonoptimal LRU decision frequency; predictable blocks; replacement policy; speculative replacement algorithm; Computer science; Counting circuits; Educational institutions; Frequency; History; Performance loss; Pollution; Runtime; System performance; Very large scale integration;
Conference_Titel :
Communications, Computers and Signal Processing, 2009. PacRim 2009. IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
978-1-4244-4560-8
Electronic_ISBN :
978-1-4244-4561-5
DOI :
10.1109/PACRIM.2009.5291234