A real-time 256×256 point two-dimensional FFT single-chip processor

Author

Miyanaga, Hiroshi ; Yamauchi, Hironori ; Matsuda, Kazuhiro

Author_Institution

NTT LSI Lab., Kanagawa, Japan

fYear

1991

fDate

14-17 Apr 1991

Firstpage

1193

Abstract

A single-chip 400-MFLOPS 2-D FFT processor VLSI architecture designed using 0.8-μm CMOS technology is proposed. This processor integrates 380000 transistors in an area of 11.58×11.58 mm² with a typical machine cycle time of 25 ns. The 24-bit floating point processor executes 2ⁿ×2ⁿ point 2-D FFT in real time, e.g., 256×256 point FFT is executed in 14 ms. This excellent performance in terms of speed and dynamic range makes the real-time processing practical for video as well as speech processing

Keywords

CMOS integrated circuits; VLSI; computerised picture processing; digital signal processing chips; fast Fourier transforms; real-time systems; speech analysis and processing; video signals; 0.8 micron; 14 ms; 2-D FFT processor; 25 ns; 400 MFLOPS; CMOS technology; VLSI architecture; machine cycle time; real-time processing; single chip processor; speech processing; transistors; video processing; CMOS technology; Digital signal processing; Dynamic range; Pipeline processing; Read-write memory; Signal processing algorithms; Signal to noise ratio; Speech processing; Very large scale integration; Video signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on

Conference_Location

Toronto, Ont.

ISSN

1520-6149

Print_ISBN

0-7803-0003-3

Type

conf

DOI

10.1109/ICASSP.1991.150595

Filename

150595