Area-aware topology generation for Application-Specific Networks-on-Chip using network partitioning

One of the challenging problems in application-specific networks-on-chip (ASNoC) design is customizing the topological structure of the on-chip network in order to meet the application requirements with the minimum possible cost. In this paper, the area cost of ASNoCs is reduced by using network partitioning techniques. Given the application core graph, the partitioning problem is formulated as an optimization one. Partitioning results in increasing the average delay, which is compensated for by adjusting the network bandwidth. A methodology is proposed for an area-aware custom topology generation employing network partitioning. As a proof of concept, our methodology is applied to three different applications with different number of cores. Results show that the proposed methodology is a promising way to reduce the ASNoC area compared to other standard and custom topology generation techniques.