Novel reciprocal and square-root VLSI cell: architecture and application to signal processing

A novel high-speed cell, capable of performing a square-root or a reciprocal function in two clock cycles, is presented. Its performance signifies an estimated three-fold increase in speed over existing approaches. Furthermore, since both functions are performed on the same cell, an area advantage of a factor of two is realized. The cell therefore has a figure of merit of six. The underlying principle used is second order interpolation which leads simultaneously to high accuracy and a very small ROM table. The statistical performance of the cell is presented. The application of the new cell is demonstrated by its use in two systolic architectures, namely an L-U decomposition architecture and a Cholesky decomposition architecture