Title :
C3L: a chip for connected component labeling
Author :
Rasquinha, Ashley ; Ranganathan, N.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
Connected component detection and labeling is an essential step in many image analysis techniques. In this paper, we propose a systolic VLSI architecture for labeling connected components in an image. The architecture has been designed and verified using Cadence Verilog-XL and also implemented on a rapid prototyping system using FPGA´s connected as a linear systolic array. Although, the algorithm has a time complexity of O(N2), this is in term of the actual clock cycle which is 15 ns. The proposed hardware can process a 128×128 image in 0.992 ms and uses 128 processors whereas the MPP requires 94.6 ms with 16384 processors
Keywords :
VLSI; application specific integrated circuits; computational complexity; digital signal processing chips; field programmable gate arrays; image processing; image processing equipment; parallel algorithms; systolic arrays; 128 pixel; 15 ns; 16384 pixel; C3L chip; Cadence Verilog-XL; DSP chip; FPGA; connected component labeling; image analysis; linear systolic array; rapid prototyping system; systolic VLSI architecture; time complexity; Hardware; Labeling; Parallel algorithms; Pixel; Registers; Systolic arrays; Very large scale integration;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568174
