Placement driven retiming with a coupled edge timing model

Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear whether the predicted performance improvement will still be valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model taking into account the effect of retiming on capacitive loads of single wires as well as fanout systems. We propose the integration of retiming into a timing-driven standard cell placement environment based on simulated annealing. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on standard FEAS (Leiserson and Saxe, J. VLSI and Computer Sys., pp. 41-67, 1983; and Algorithmica vol. 6, no 1, pp. 5-35, 1991.), our approach achieved an improvement in cycle time of up to 34% and 17% on the average.