Interconnect resource-aware placement for hierarchical FPGAs

Author

Singh, A. ; Parthasarathy, G. ; Marek-Sadowska, M.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

fYear

2001

fDate

4-8 Nov. 2001

Firstpage

132

Lastpage

136

Abstract

Utilizes Rent´s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design complexity and architecture resources of hierarchical FPGAs can have a positive impact on the overall device area. We propose a circuit placement algorithm based on Rent´s parameter and show that our clustering and placement techniques can improve the overall device routing area by as much as 21% for the same array size, when compared to a state-of-art FPGA placement and routing tool.

Keywords

circuit layout CAD; delays; field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; logic CAD; logic gates; network routing; Rent´s rule; architecture resources; array size; circuit placement algorithm; clustering; design complexity; empirical measure; hierarchical FPGAs; interconnect resource-aware placement; overall device area; Clustering algorithms; Computer architecture; Cost function; Delay; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Routing; Steiner trees; Tree graphs;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on

Conference_Location

San Jose, CA, USA

ISSN

1092-3152

Print_ISBN

0-7803-7247-6

Type

conf

DOI

10.1109/ICCAD.2001.968609

Filename

968609