Title :
Micropipeline architecture for multiplier-less FIR filters
Author :
Nooshabadi, S. ; Montiel-Nelson, J.A. ; Visweswaran, G.S. ; Nagchoudhurhi, D.
Author_Institution :
Sch. of Electr. Eng., Northern Territory Univ., Casuarina, NT, Australia
Abstract :
In this paper asynchronous design techniques are employed to implement a multiplierless FIR filter. Suitability of modular, micropipelined based design style for mapping of the DSP algorithms into VLSI hardware has been demonstrated. In this design global clock has been eliminated, thereby, reducing the complexity associated with the clock distribution network
Keywords :
FIR filters; VLSI; asynchronous circuits; delays; digital filters; pipeline processing; timing; DSP algorithms; VLSI hardware; asynchronous design techniques; global clock elimination; micropipeline architecture; modular micropipelined based design style; multiplier-less FIR filters; CMOS logic circuits; CMOS technology; Clocks; Computer architecture; Delay; Finite impulse response filter; Hardware; Synchronization; Timing; Very large scale integration;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568175
