Accelerating FPGA development through the automatic parallel application of standard implementation tools

FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. As in many multithreaded applications, communication and synchronization incur significant overheads. Even if these challenges are overcome, the large graph data structures used can quickly exhaust memory bandwidth as more cores are employed. We approach the problem in a different way for development environments in which some circuit speed and area optimization may be sacrificed for improved implementation and debug turnaround. The PATIS automatic floorplanner enables dynamic modular design. While existing modular and incremental flows facilitate timing closure late in the design cycle by reusing the layout of unmodified blocks, dynamic modular design accelerates non-local changes to the physical layout arising from design exploration and the addition of debug circuitry. A PATIS floorplan consists of partial modules with structured physical interfaces observable through configuration readback, allowing module ports to be passively probed without disturbing the layout. Although PATIS supports incremental design, global changes are still rapid because each block´s partial bitstream is produced by independent and concurrent invocations of the standard Xilinx tools running on separate cores or hosts. A continuous background task proactively generates floorplan variants to further accelerate layout changes.