ASIP-controlled Inverse Integer Transform for H.264/AVC Compression

In this paper, an application-specific instruction set processor (ASIP) -controlled inverse integer transform IP block on a system-on-chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4times4 and 8times8 inverse integer transform with additional support for 2times2 and 4times4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4times4 circuit in the 8times8 circuit, while achieving a speed of 176 MHz.